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? semiconductor components industries, llc, 2003 september, 2003 ? rev. 1 1 publication order number: and8123/d and8123/d power factor correction stages operating in critical conduction mode prepared by: joel turchi on semiconductor this paper pr oposes a detailed and mathematical analysis of the operation of a critical conduction mode power factor corrector (pfc), with the goal of easing the pfc stage dimensioning. after some words on the pfc specification and a brief presentation of the main critical conduction schemes, this application note gives the equations necessary for computing the magnitude of the currents and voltages that are critical in the choice of the power components. introduction the iec1000?3?2 specification, usually named power factor correction (pfc) standard, has been issued with the goal of minimizing the total harmonic distortion (thd) of the current that is drawn from the mains. in practice, the legislation requests the current to be nearly sinusoidal and in phase with the ac line voltage. active solutions are the most effective means to meet the legislation. a pfc pre?regulator is inserted between the input bridge and the bulk capacitor. this intermediate stage is designed to output a constant voltage while drawing a sinusoidal current from the line. in practice, the step?up (or boost) configuration is adopted, as this type of converter is easy to implement. one can just notice that this topology requires the output to be higher than the input voltage. that is why the output regulation level is generally set to around 400 v in universal mains conditions. basics of the critical conduction mode critical conduction mode (or border line conduction mode) operation is the most popular solution for low power applications. characterized by a variable frequency control scheme in which the inductor current ramps to twice the desired average value, ramps down to zero, then immediately ramps positive again (refer to figures 2 and 4), this control method has the following advantages: ? simple control scheme: the application requires few external components. ? ease of stabilization: the boost keeps a first order converter and there is no need for ramp compensation. ? zero current turn on: one major benefit of critical conduction mode is the mosfet turn on when the diode current reaches zero. therefore the mosfet switch on is lossless and soft and there is no need for a low trr diode. on the other hand, the critical conduction mode has some disadvantages: ? large peak currents that result in high dl/dt and rms currents conducted throughout the pfc stage. ? large switching frequency variations as detailed in the paper. diode bridge in + ? ac line controller + bulk capacitor load pfc stage power supply figure 1. power factor corrected power converter pfc boost pre?converters typically require a coil, a diode and a power switch. this stage also needs a power factor correction controller that is a circuit specially designed to drive pfc pre?regulators. on semiconductor has developed three controllers (mc33262, mc33368 and MC33260) that operate in critical mode and the ncp1650 for continuous mode applications. one generally devotes critical conduction mode to power factor control circuits below 300 w. application note http://onsemi.com
and8123/d http://onsemi.com 2 diode bridge in + ? figure 2. switching sequences of the pfc stage v in l icoil diode bridge in + ? v in l + v out the power switch is on the power switch is off the power switch being about zero, the input voltage is applied across the coil. the coil current linearly increases with a (v in /l) slope. the coil current flows through the diode. the coil voltage is (v out ?v in ) and the coil current linearly decays with a (v out ?v in )/l slope. critical conduction mode: next current cycle starts as soon as the core is reset. (v out ?v in )/l icoil_pk v in /l coil current icoil in critical discontinuous mode, a boost converter presents two phases (refer to figure 2): ? the on?time during which the power switch is on. the inductor current grows up linearly according to a slope (v in /l) where v in is the instantaneous input voltage and l the inductor value. ? the off time during which the power switch is off. the inductor current decreases linearly according to the slope (v out ?v in )/l where v out is the output voltage. this sequence terminates when the current equals zero. consequently, a triangular current flows through the coil. the pfc stage adjusts the amplitude of these triangles so that in average, the coil current is a (rectified) sinusoid (refer to figure 4). the emi filter (helped by the 100 nf to 1.0 f input capacitor generally placed across the diodes bridge output), performs the filtering function. the more popular scheme to control the triangles magnitude and shape the current, forces the inductor peak current to follow a sinusoidal envelope. figure 3 diagrammatically portrays its operation mode that could be summarized as follows: ? the diode bridge output being slightly filtered, the input voltage (v in ) is a rectified sinusoid. one pin of the pfc controller receives a portion of v in . the voltage of this terminal is the shaping information necessary to build the current envelope. ? an error amplifier evaluates the power need in response to the error it senses between the actual and wished levels of the output voltage. the error amplifier bandwidth is set low so that the error amplifier output reacts very slowly and can be considered as a constant within an ac line period. ? the controller multiplies the shaping information by the error amplifier output voltage. the resulting product is the desired envelope that as wished, is sinusoidal, in phase with the ac line and whose amplitude depends on the amount of power to be delivered. ? the controller monitors the power switch current. when this current exceeds the envelope level, the pwm latch is reset to turn off the power switch. ? some circuitry detects the core reset to set the pwm latch and initialize a new mosfet conduction phase as soon as the coil current has reached zero. consequently, when the power switch is on, the current ramps up from zero up to the envelope level. at that moment, the power switch turns off and the current ramps down to zero (refer to figures 2 and 4). for simplicity of the drawing, figure 4 only shows 8 acurrent triangleso. actually, their frequency is very high compared to the ac line one. the input filtering capacitor and the emi filter averages the atriangleso of the coil current, to give: icoil t icoil_pk 2 (eq. 1) where t is the average of one current triangle (period t) and icoil_pk is the peak current of this triangle.
and8123/d http://onsemi.com 3 as icoil_pk is forced to follow a sinusoidal envelop (k*v in ), where k is a constant modulated by the error amplifier, t is also sinusoidal icoil t k*vin 2 k* 2 * vac * sin( t) 2 . as a result, this scheme makes the ac line current sinusoidal. v in pfc stage ac line input filtering capacitor l1 x1 r7 current sensing resistor zero current detection s r q pwm latch + - output buffer current envelope current sense comparator multiplier + - vref error amplifier r1 r2 c2 r3 r4 d1 + c1 bulk capacitor figure 3. switching sequences of the pfc stage the controller monitors the input and output voltages and using this information and a multiplier, builds a sinusoidal envelope . when the sensed current exceeds the envelope level, the current sense comparator resets the pwm latch and the power switch turns off. on ce the core has reset, a dedicated block sets the pwm latch and a new mosfet conduction time starts.
and8123/d http://onsemi.com 4 icoil_pk average ( t ) peak inductor current (icoil) mosfet drive tac/2 (tac is the ac line period) t figure 4. coil current during the power switch conduction time, the current ramps up from zero up to the envelope level. at that moment, the power switch turns off and the current ramps down to zero. for simplicity of the drawing, only 8 acurrent triangleso are shown. actually, their frequency is very high compared to the ac line one. one can note that a simple calculation would show that the on?time is constant over the sinusoid: ton 2*l* pin vac 2 and that the switching frequency modulation is brought by the off?time that equals: toff 2* 2 *l* pin vac * (vout 2 * vac * sin( t)) * sin( t) ton * 2 *vac*sin( t) vout 2 * vac * sin( t) (eq. 2) that is why the MC33260 developed by on semiconductor does not incorporate a multiplier inputting a portion of the rectified ac line to shape the coil current. instead, this part forces a constant on?time to achieve in a simplest manner, the power factor correction. main equations switching frequency as already stated, the coil current consists of two phases: ? the power switch conduction time (ton). during this time, the input voltage applies across the coil and the current increases linearly through the coil with a (v in /l) slope: icoil(t) vin l *t (eq. 3) this phase ends when the conduction time (ton) is complete that is when the coil current has reached its peak value (icoil_pk). thus: icoil_pk vin l *ton (eq. 4) the conduction time is then given by: ton l * icoil_pk vin (eq. 5) ? the power switch off time (toff). during this second phase, the coil current flows through the output diode and feeds the output capacitor and the load. the diode voltage being considered as null when on, the voltage across the coil becomes negative and equal to (v in ?v out ). the coil current decreases then linearly with the slope ((v out ?v in )/l) from (icoil_pk) to zero, as follows: icoil(t) icoil_pk vout vin l *t (eq. 6) this phase ends when icoil reaches zero, then the of f?time is given by the following equation: toff l * icoil_pk vout vin (eq. 7) the total current cycle (and then the switching period, t) is the sum of ton and toff. thus: t ton toff l * icoil_pk * vout vin * (vout vin) (eq. 8)
and8123/d http://onsemi.com 5 as shown in the next paragraph (equation 15), the coil peak current can be expressed as a function of the input power and the ac line rms voltage as follows: icoil_pk 2* 2 * pin vac * sin( t) , where is the ac line angular frequency. replacing icoil_pk by this expression in equation (8) leads to: t 2* 2 * l* pin vac * sin( t) (eq. 9) * vout 2 * vac * sin( t) * (vout vin) this equation simplifies: t 2*l* pin * vout vac 2 * (vout vin) (eq. 10) the switching frequency is the inverse of the switching period. consequently: f vac 2 2*l* pin 1 2 *vac*sin( t) vout (eq. 11) this equation shows that the switching frequency consists of: ? one term vac 2 2*l* pin that only varies versus the working point (load and ac line rms voltage). ? a modulation factor 1 2 * vac * sin( t) vout that makes the switching frequency vary within the ac line sinusoid. the following figure illustrates the switching frequency variations versus the ac line amplitude, the power and within the sinusoid. figure 5. switching frequency over the ac line rms voltage (at the sinusoid top) the figure represents the switching frequency variations versus the line rms voltage, in a normalized form where f(90) = 1. the plot drawn for v out = 400 v, shows large variations (200% at vac = 180 v, 60% at vac = 270 v). the shape of the curve tends to flatten if v out is higher. however, the minimum of the switching frequency is always obtained at one of the ac line extremes (vacll or vachl where vacll and vachl are respectively, the lowest and highest vac levels). 80 2.50 f / f(90) v ac , (v) 110 140 170 200 230 260 290 2.00 1.50 1.00 0.50 figure 6. switching frequency vs. the input power (at the sinusoid top) this plot sketches the switching frequency variations versus the input power in a normalized form where f(200 w) = 1. the switching frequency is multiplied by 20 when the power is 10 w. in practice, the pfc stage propagation delays clamp the switching frequency that could theoretically exceed several megahertz in very light load conditions. the MC33260 minimum off?time limits the no load frequency to around 400 khz. 0 20 f / f(200w) pin (w) 50 100 150 200 10 0 figure 7. switching frequency over the ac line sinusoid @ 230 vac this plot gives the switching variations over the ac line sinusoid at vac = 230 v and v out = 400 v, in a normalized form where f is taken equal to 1 at the ac line zero crossing. the switching frequency is approximately divided by 5 at the top of the sinusoid. 0 1.5 t 1.0 2.0 3.0 1.0 0.5 0 f sin ( t)
and8123/d http://onsemi.com 6 figure 8. switching frequency over the ac line sinusoid @ 90 vac this plot shows the same characteristic but for vac = 90 v. similarly to what was observed in figure 5 (f versus vac), the higher the difference between the output and input voltages, the flatter the switching frequency shape. 0 1.5 t 1.0 2.0 3.0 1.0 0.5 0 f sin ( t) finally, the switching frequency dramatically varies within the ac line and versus the power. this is probably the major inconvenience of the critical conduction mode operation. this behavior often makes tougher the emi filtering. it also can increase the risk of generating interference that disturb the systems powered by the pfc stage (for instance, it may produce some visible noise on the screen of a monitor). in addition, the variations of the frequency and the high values it can reach (up to 500 khz) practically prevent the use of effective tools to damp emi and reduce noise like snubbing networks that would generate too high losses. one can also note that the frequency increases when the power diminishes and when the input voltage increases. in light load conditions, the switching period can become as low as 2.0 s (500 khz). all the propagation delays within the control circuitry or the power switch reaction times are no more negligible, what generally distorts the current shape. the power factor is then degraded. the switching frequency variation is a major limitation of the system that should be reserved to application where the load does not vary drastically. coil peak and rms currents coil peak current as the pfc stage makes the ac line current sinusoidal and in phase with the ac line voltage, one can write: lin(t) 2 * lac * sin( t) (eq. 12) where iin(t) is the instantaneous ac line current and iac its rms value. provided that the ac line current results from the averaging of the coil current, one can deduct the following equation: lin(t) icoil t icoil_pk 2 (eq. 13) where t is the average of the considered coil current triangle over the switching period t and icoil_pk is the corresponding peak. thus, the peak value of the coil current triangles follows a sinusoidal envelope and equals: icoil_pk 2* 2 * lac * sin( t) (eq. 14) since the pfc stage forces the power factor close to 1, one can use the well known relationship linking the average input power to the ac line rms current and rms voltage ( pin vac * lac) and the precedent equation leads to: (eq. 15) icoil_pk 2* 2 * pin vac * sin( t) the coil current peak is maximum at the top of the sinusoid where sin(
t) 1 . this maximum value, (icoil_pk)h, is then: (eq. 16) (icoil_pk)h 2* 2 * pin vac from this equation, one can easily deduct that the peak coil current is maximum when the required power is maximum and the ac line at its minimum voltage: (eq. 17) icoil_max 2 * 2 * pin max vacll where max is the maximum input power of the application and vacll the lowest level of the ac line voltage. coil rms current the rms value of a current is the magnitude that squared, gives the dissipation produced by this current within a 1.0 resistor. one must then compute the rms coil current by: ? first calculating the arms currento within a switching period in such a way that once squared, it would give the power dissipated in a 1.0 resistor during the considered switching period. ? then the switching period being small compared to the input voltage cycle, regarding the obtained expression as the instantaneous square of the coil current and averaging it over the rectified sinusoid cycle, to have the squared coil rms current. this method will be used in this section. as above explained, the current flowing through the coil is: ? (i m (t) vin * t l icoil_pk * t ton) during the mosfet on?time, when 0 and8123/d http://onsemi.com 7 therefore, the rms value of any coil current triangle over the corresponding switching period t, is given by the following equation: (icoil)rms t 1 t * ton 0
icoil_pk * t ton 2 *dt t ton
icoil_pk * t t t ton 2 *dt (eq. 18) solving the integrals, it becomes: (icoil)rms t 1 t *
icoil_pk 2 ton 2 * ton 3 3
(t ton) 3 * icoil_pk *
icoil_pk * t t t ton 3
icoil_pk * t ton t ton 3 (eq. 19 ) the precedent simplifies as follows: (icoil)rms t 1 t * icoil_pk 2 *ton 3
(t ton) 3 * icoil_pk * ( icoil_pk 3 ) (eq. 20) rearrangement of the terms leads to: (icoil)rms t i coil_pk * 1 t * ton 3 t ton 3 (eq. 21) calculating the term under the root square sign, the following expression is obtained: (icoil)rms t icoil_pk 3 (eq. 22) replacing the coil peak current by its expression as a function of the average input power and the ac line rms voltage (equation 15), one can write the following equation: (icoil)rms t 2* 2 3 * pin vac * sin( t) (eq. 23) this equation gives the equivalent rms current of the coil over one switching period, that is, at a given v in . as already stated, multiplying the square of it by the coil resistance, gives the resistive losses at this given v in . now to have the rms current over the rectified ac line period, one must not integrate <(icoil)rms> t but the square of it, as we would have proceeded to deduct the average resistive losses from the dissipation over one switching period. however, one must not forget to extract the root square of the result to obtain the rms value. as the consequence, the coil rms current is: (icoil)rms 2 tac * tac 2 0 (i coil )rms t 2 *dt (eq. 24) where tac = 2* / is the ac line period (20 ms in europe, 16.66 ms in usa). the pfc stage being fed by the rectified ac line voltage, it operates at twice the ac line frequency. that is why, one integrates over half the ac line period (tac/2). substitution of equation (23) into the precedent equation leads to: (eq. 25) (icoil)rms 2 tac * tac 2 0
2* 2 3 * pin vac * sin( t) 2 *dt this equation shows that the coil rms current is the rms value of: 2* 2 3 * pin vac * sin( t) , that is, the rms value of a sinusoidal current whose magnitude is (2 * 2 3 * pin vac ) . the rms value of such a sinusoidal current is well known (the amplitude divided by 2 ). therefore: icoil(rms) 2 3 * pin vac (eq. 26)
and8123/d http://onsemi.com 8 switching losses the switching losses are difficult to determine with accuracy. they depend of the mosfet type and in particular of the gate charge, of the controller driver capability and obviously of the switching frequency that varies dramatically in a critical conduction mode operation. however, one can make a rough estimation if one assumes the following: ? the output voltage is considered as a constant. the output voltage ripple being generally less than 5% the nominal voltage, this assumption seems reasonable. ? the switching times ( t and t fr , as defined in figure 9), are considered as constant over the sinusoid. figure 9. turn off waveforms dissipated power: (i mosfet * vdrain) i mosfet vdrain t t fr figure 9 represents a turn off sequence. one can observe three phases: ? during approximately the second half of the gate voltage miller plateau, the drain?source voltage increases linearly till it reaches the output voltage. ? during a short time that is part of the diode forward recovery time, the mosfet faces both maximum voltage and current. ? the gate voltage drops (from the miller plateau) below the gate threshold and the drain current ramps down to zero. a to of figure 9 represents the total time of the three phases, at fr '' the second phase duration. therefore, one can write: psw vout * icoil_pk 2 * t?t fr t vout * icoil_pk * t fr t (eq. 27) where: t and t fr are the switching times portrayed by figure 9 and t is the switching period. equation (8) gives an expression linking the coil peak current and the switching period of the considered current cycle (triangle): t l * icoil_pk vin * vout vout vin . substitution of equation (8) into the equation (27) leads to: psw vin * (vout vin) * ( t t fr ) 2*l (eq. 28)
and8123/d http://onsemi.com 9 this equation shows that the switching losses over a switching period depend of the instantaneous input voltage, the difference between the instantaneous output and input voltages, the switching time and the coil value. let's calculate the average losses () by integrating psw over half the ac line period: (eq. 29) psw 2 tac * tac 2 0 vin * (vout vin) * ( t t fr ) 2*l *dt rearranging the terms, one obtains: (eq. 30) psw t t fr 2*l * 2 tac * tac 2 0 vin * vout * dt 2 tac * tac 2 0 vin 2 *dt v out being considered as a constant, one can easily solve this equation if one remembers that the input voltage average value is (2 * 2 *vac ) and that (vac 2 2 tac * tac 2 0 vin 2 *dt) . applying this, it becomes: (eq. 31) psw t t fr 2*l * 2* 2 * vac * vout vac 2 or in a simpler manner: (eq. 32) psw 2*( t t fr )*vac 2 *l * vout 2 * vac 4 the coil inductance (l) plays an important role: the losses are inversely proportional to this value. it is simply because the switching frequency is also inversely proportional to l. this equation also shows that the switching losses are independent of the power level. one could have easily predict this result by simply noting that the switching frequency increased when power diminished. equation (32) also shows that the lower the ratio (v out /vac), the smaller the mosfet switching losses. that is because the afollower boosto mode that reduces the difference between the output and input voltages, lowers the switching frequency. in other words, this technique enables the use of a smaller coil for the same switching frequency range and the same switching losses. for instance, the MC33260 features the afollower boosto operation where the pre?converter output voltage stabilizes at a level that varies linearly versus the ac line amplitude. this technique aims at reducing the gap between the output and input voltages to optimize the boost efficiency and minimize the cost of the pfc stage 1 . how to extract t and t fr ? ? the best is to measure them. ? one can approximate t as the time necessary to extract the gate charge q3 of the mosfet (refer to figure 10). q3 being not always specified, instead, one can take the sum of q1 with half the miller plateau gate charge (q2/2). knowing the drive capability of the circuit, one can deduct the turn off time ( t = q3/i drive or t = [q1 + (q2/2)]/i drive ). ? in a first approach, t fr can be taken equal to the diode forward recovery time. figure 10. typical total gate charge specification of a mosfet v ds , drain-to-source voltage (volts) v gs , gate-to-source voltage (volts) q t , total gate charge (nc) i d = 2.3 a t j = 25 c 3 0 12 9 6 qt q1 q3 v gs v ds q2 one must note that the calculation does not take into account: ? the energy consumed by the controller to drive the mosfet (qcc*vcc*f), where qcc is the mosfet gate charge necessary to charge the gate voltage to vcc, vcc the driver supply voltage and f the switching frequency. ? the energy dissipated because of the parasitic capacitors of the pfc stage. each turn on produces an abrupt voltage change across the parasitic capacitors of the mosfet drain?source, the diode and the coil. this results in some extra dissipation across the mosfet (1/2*c parasitic * v 2 *f), where c parasitic is the
and8123/d http://onsemi.com 10 considered parasitic capacitor and v the voltage change across it. 1 refer to MC33260 data sheet for more details at http://www.onsemi.com/. however, equation (32) should give a sufficient first approach approximation in most applications where the two listed sources of losses play a minor role. nevertheless, the losses produced by the parasitic capacitors may become significant in light load conditions where the switching frequency gets high. as always, bench validation is key. power mosfet conduction losses as portrayed by figure 4, the coil current is formed by high frequency triangles. the input capacitor together with the input rfi filter integrates the coil current ripple so that the resulting ac line current is sinusoidal. during the on?time, the current rises linearly through the power switch as follows: icoil(t) vin l *t (eq. 33) where v in is the input voltage (vin 2 * vac * sin( t) ) , l is the coil inductance and t is the time. during the rest of the switching period, the power switch is off. the conduction losses resulting from the power dissipated by icoil during the on?time, one can calculate the power during the switching period t as follows: (eq. 34) p t 1 t * ton 0 ron * icoil(t) 2 *dt 1 t * ton 0 ron * vin l *t 2 *dt where ron is the mosfet on?time drain source resistor, ton is the on?time. solving the integral, equation (34) simplifies as follows: p t ron t * vin l 2 * ton 0 t 2 *dt 1 3 *ron* vin l 2 * ton 3 t (eq. 35) as the coil current reaches its peak value at the end of the on?time, icoil_pk vin * ton l and the precedent equation can be rewritten as follows: (eq. 36) p t 1 3 * ron * icoil_pk 2 * ton t one can recognize the traditional equation permitting to calculate the mosfet conduction losses in a boost or a flyback ( 1 3 * ron * ipk 2 *d , where ipk is the peak current and d, the mosfet duty cycle). one can calculate the duty cycle (d = ton/t) by: ? either noting that the off?time (toff) can be expressed as a function of ton (refer to equation 2) and substituting this equation into (t = ton + toff), ? or considering that the critical conduction mode being at the border of the continuous conduction mode (ccm), the expression giving the duty?cycle in a ccm boost converter applies. both methods lead to the same following result: d ton t 1 vin vout (eq. 37) substitution of equation (37) into equation (36) leads to: p t 1 3 * ron * icoil_pk 2 * 1 vin vout (eq. 38) one can note that the coil peak current (icoil_pk) that follows a sinusoidal envelop, can be written as follows: icoil_pk 2* 2 * pin vac * sin( t) (refer to equation 15). replacing v in and icoil_pk by their sinusoidal expression, respectively (2 * vac * sin( t) ) and (2 * 2 * pin vac * sin( t) ) , equation (38) becomes: (eq. 39) p t 1 3 *ron* 2* 2 * pin vac * sin( t) 2 * 1 2 * vac * sin( t) vout that is in a more compact form: (eq. 40) p t 8 3 *ron* pin vac 2 *
sin 2 ( t) 2 *vac vout * sin 3 ( t) equation (40) gives the conduction losses at a given v in voltage. this equation must be integrated over the rectified ac line sinusoid to obtain the average losses: (eq. 41) p tac 8 3 *ron* pin vac 2 * 2 tac * tac 2 0
sin 2 ( t) 2 *vac vout * sin 3 ( t) *dt
and8123/d http://onsemi.com 11 if the average value of sin 2 ( t) is well known (0.5), the calculation of requires few trigonometry remembers: ? sin 2 ( ) 1 cos(2 ) 2 ? sin( ) * cos( ) sin( ) sin( ) 2 combining the two precedent formulas, one can obtain: sin 3 ( t) 3 * sin( t) 4 sin(3 t) 4 (eq. 42) substitution of equation 42) into equation (41) leads: (eq. 43) p tac 8 3 *ron* pin vac 2 * 2 tac * tac 2 0
sin( t) 2 3* 2 *vac 4 * vout * sin( t) 2 *vac 4 * vout * sin(3 t) *dt solving the integral, it becomes: (eq. 44) p tac 8 3 *ron* pin vac 2 *
1 2 3* 2 *vac 4 * vout * 2 2 *vac 4 * vout * 2 3 equation (44) simplifies as follows: (eq. 45) p tac 4 3 * ron * pin vac 2 *
1 8* 2 *vac 3 * vout this formula shows that the higher the ratio (vac/v out ), the smaller the mosfet conduction losses. that is why the afollower boosto mode that reduces the difference between the output and input voltages, enables to reduce the mosfet size. for instance, the MC33260 features the afollower boosto operation where the pre?converter output voltage stabilizes at a level that varies linearly versus the ac line amplitude. this technique aims at reducing the gap between the output and input voltages to optimize the boost efficiency and minimize the cost of the pfc stage 2 . by the way, one can deduct from this equation the rms current ((i m )rms) flowing through the power switch knowing that p tac ron * (i m ) 2 rms : (i m )rms 2 3 * pin vac * 1 8* 2 *vac 3 * vout (eq. 46) dissipation within the current sense resistor pfc controllers monitor the power switch current either to perform the shaping function or simply to prevent it from being excessive. that is why a resistor is traditionally placed between the mosfet source and ground to sense the power switch current. 2 refer to MC33260 data sheet for more details at http://www.onsemi.com/. the MC33260 monitors the whole coil current by monitoring the voltage across a resistor inserted between ground and the diodes bridge (negative sensing refer to figure 15). the circuit utilizes the current information for both the overcurrent protection and the core reset detection (also named zero current detection). this technique brings two major benefits: ? no need for an auxiliary winding to detect the core reset. a simple coil is sufficient in the pfc stage. ? the MC33260 detects the in?rush currents that may flow at start?up or during some overload conditions and prevents the power switch from turning on in that stressful condition. the pfc stage is significantly safer. some increase of the power dissipated by the current sense resistor is the counter part since the whole current is sensed while circuits like the mc33262 only monitor the power switch current. dissipation of the current sense resistor in mc33262 like circuits since the same current flows through the current sense resistor and the power switch, the calculation is rather easy. one must just square the rms value of the power switch current (i m )rms calculated in the previous section and multiply the result by the current sense resistance.
and8123/d http://onsemi.com 12 doing this, one obtains: prs 262 4 3 * rs * pin vac 2 *
1 8* 2 *vac 3 * vout (eq. 47) where 262 is the power dissipated by the current sense resistor rs. dissipation of the current sense resistor in MC33260 like circuits in this case, the current sense resistor rs derives the whole coil current. consequently, the product of rs by the square of the rms coil current gives the dissipation of the current sense resistor: prs 260 rs * (icoil(rms) ) 2 (eq. 48) where icoil(rms) is the coil rms current that as expressed by equation (26), equals: icoil(rms) 2 3 * pin vac . consequently: prs 260 4*rs 3 * pin vac 2 (eq. 49) comparison of the losses amount in the two cases let's calculate the ratios: prs 262 prs 260 . one obtains: (eq. 50) prs 262 prs 260 1 8* 2 *vac 3 * vout if one considers that (8/3 ) approximately equals 0.85, the precedent equation simplifies: (eq. 51) prs 262 prs 260 1 0.85 * vm vout where vm is the ac line amplitude. average and rms current through the diode the diode average current can be easily computed if one notes that it is the sum of the load and output capacitor currents: (eq. 52) id i load i cout then, in average: (eq. 53) id i load i cout i load i cout at the equilibrium, the average current of the output capacitor must be 0 (otherwise the capacitor voltage will be infinite). thus: (eq. 54) id i load pout vout the rms diode current is more difficult to calculate. similarly to the computation of the rms coil current for instance, it is necessary to first compute the squared rms current at the switching period level and then to integrate the obtained result over the ac line sinusoid. as portrayed by figure 4, the coil discharges during the off time. more specifically, the current decays linearly through the diode from its peak value (icoil_pk) down to zero that is reached at the end of the off?time. taking the beginning of the off?time as the time origin, one can then write: (eq. 55) icoil(t) icoil_pk * toff?t toff similarly to the calculation done to compute the coil rms current, one can calculate the adiode rms current over one switching periodo: (eq. 56) id(rms) 2 t 1 t * toff 0
icoil_pk * toff?t toff 2 *dt solving the integral, one obtains the expression of the arms diode current over one switching periodo: (eq. 57) id(rms) t toff 3*t * icoil_pk substitution of equation (15) that expresses icoil_pk, into the precedent equation leads to: (eq. 58) id(rms) t 2* 2 3 * pin vac * toff t * sin( t) in addition, one can easily show that toff and t are linked by the following equation: (eq. 59) toff t* vin vout t* 2 * vac * sin( t) vout consequently, equation (58) can be changed into: (eq. 60) id(rms) t 2* 2* 2 3 * pin vac * vout * sin( t) 3 this equation gives the equivalent rms current of the diode over one switching period, that is, at a given v in . as already stated in the coil peak and rms currents section, the square of this expression must be integrated over a rectified sinusoid period to obtain the square of the diode rms current. therefore: (eq. 61) id(rms) 2 2 tac * tac 2 0 8* 2 3 * pin 2 vac * vout * sin 3 ( t) * dt
and8123/d http://onsemi.com 13 similarly to the power mosfet conduction losses section, the integration of (sin 3 ( t)) requires some preliminary trigonometric manipulations: sin 3 ( t) sin( t) * sin 2 ( t) sin( t) * 1 cos(2 t) 2 1 2 * sin( t) 1 2 * sin( t) * cos(2 t) sin( t) * cos(2 t) 1 2 * (sin(? t) sin(4 t) ) sin 3 ( t) 3 4 * sin( t) 1 4 * sin(3 t) and : then : consequently, equation (61) can change into: (eq. 62) id(rms) 2 2 tac * tac 2 0 8* 2 3 * pin 2 vac * vout *
3 * sin( t) 4 sin(3 t) 4 *dt one can now solve the integral and write: (eq. 63) id(rms) 2 16 * 2 3 * tac * pin 2 vac * vout * 3*(cos( 0) cos( tac 2) ) 4 cos(3 tac 2) cos(3 0) 12 as (
*tac 2 ) , we have: (eq. 64) id(rms) 2 16 * 2 3 * pin 2 vac * vout * 3 * (1? cos( )) 4 *tac cos( )?1 12 *tac one can simplify the equation replacing the cosine elements by their value: (eq. 65) id(rms) 2 16 * 2 3 * pin 2 vac * vout * 6 8* 1 12 * the square of the diode rms current simplifies as follows: (eq. 66) id(rms) 2 32 * 2 9* * pin 2 vac * vout finally, the diode rms current is given by: (eq. 67) id(rms) 4 3 * 2* 2 * pin vac * vout output capacitor rms current as shown by figure 11, the capacitor current results from the difference between the diode current (i1) and the current absorbed by the load (i2): (eq. 68) ic(t) i1(t) i2(t) thus, the capacitor rms current over the rectified ac line period, is the rms value of the difference between i1 and i2 during this period. as a consequence: (eq. 69) ic(rms) 2 2 tac * tac 2 0 (i1 i2) 2 *dt rearranging (i1?i2) 2 leads to: (eq. 70) ic(rms) 2 2 tac * tac 2 0 [i1 2 i2 2 (2 * i1 * i2)] * dt thus: (eq. 71) ic(rms) 2 i1(rms) 2 i2(rms) 2 4 tac * tac 2 0 i1 * i2 * dt figure 11. output capacitor current pfc stage v in load ld v out i1 i2 ic drv power switch one knows the first term (i1(rms) 2 ) . this is the diode rms current calculated in the previous section. the second and third terms are dependent of the load. one cannot compute them without knowing the characteristic of this load. anyway, the second term (i2(rms) 2 ) is generally easy to calculate once the load is known. typically, this is the rms current absorbed by a downstream converter. on the other hand, the third term is more difficult to determine as it depends on the relative occurrence of the i1 and i2 currents. as the pfc stage and the load (generally a switching mode power supply) are not synchronized, this term even seems impossible to predict. one can simply note that this term tends to decrease the capacitor rms current and consequently, one can deduct that: (eq. 72) ic(rms) i1(rms) 2 i2(rms) 2
and8123/d http://onsemi.com 14 substitution of equation (67) that gives the diode rms current into the precedent equation leads to: (eq. 73) ic(rms) 32 * 2 * pin 2 9* *vac*vout i2(rms) 2 where i2(rms) is the load rms current. (eq. 74) ic(rms) 2 1(rms) 2 vout r 2 4 tac * tac 2 0 1* vout r *dt if the load is resistive, i2 = v out /r where r is the load resistance and equation (71) changes into: thus, the capacitor squared rms current is: ic(rms) 2 32 * 2 9* * pin 2 vac * vout vout r 2 2 * vout r * pout vout as pout = v out 2 /r, the precedent equation simplifies as follows: ic(rms)
32 * 2 9* * pin 2 vac * vout vout r 2 (eq. 75) ic(rms) 2 id(rms) 2 vout r 2 2 * vout r * id (eq. 76) (eq. 77) you may find a more friendly expression in the literature: ic(rms) i2 2 , where i2 is the load current. this equation is an approximate formula that does not take into account the switching frequency ripple of the diode current. only the low frequency current that generates the low frequency ripple of the bulk capacitor (refer to the next section) is considered (this expression can easily be found by using equation (88) and computing ibulk cbulk * dvout dt ). equation (77) takes into account both high and low frequency ripples. output voltage ripple the output voltage (or bulk capacitor voltage) exhibits two ripples. the first one is traditional to switch mode power supplies. this ripple results from the way the output is fed by current pulses at the switching frequency pace. as bulk capacitors exhibit a parasitic series resistor (esr refer to figure 12), they cannot fully filter this pulsed energy source. more specifically: ? during the on?time, the pfc mosfet conducts and no energy is provided to the output. the bulk capacitor feeds the load with the current it needs. the current together with the esr resistor of the bulk capacitor form a negative voltage (esr*i2), where i2 is the instantaneous load current, ? during the off?time, the diode derives the coil current towards the output and the current across the esr becomes esr*(id?i2), where id is the instantaneous diode current. this explanation assumes that the energy that is fed by the pfc stage perfectly matches the energy drawn by the load over each switching period so that one can consider that the capacitive part of the bulk has a constant voltage and that only the esr creates some ripple. in fact, there is an additional low frequency ripple which is inherent to the power factor correction. the input current and voltage being sinusoidal, the power fed by the pfc stage has a squared sinusoid shape. on the other hand, the load generally draws a constant power. as a consequence, the pfc pre?converter delivers an amount of power that matches the load demand in average only. the output capacitor compensates the lack (excess) of input power by supplying (storing) the part of energy necessary for the instantaneous matching. figures 13 and 14 sketch this behavior. figure 12. esr of the output capacitor pfc stage v in load id i2 ic esr bulk capacitor driver
and8123/d http://onsemi.com 15 figure 13. output voltage ripple the dashed black line represents the power that is absorbed by the load. the pfc stage delivers a power that has a squared sinusoid shape. as long as this power is lower than the load demand, the bulk capacitor compensates by supplying part of the energy it stores. consequently the output voltage decreases. when the power fed by the pfc pre?converter exceeds the load consumption, the bulk capacitor recharges. the peak of the pfc power is twice the load demand. load power (100 w) *pin (40 w/div) vout (5 v/div) 400 v vin (100 v/div) 0 v figure 14. output voltage ripple vin (100 v/div) ic (200 ma/div) vout (5 v/div) 400 v 0 a 0 v the output voltage equals its average value when the input voltage is minimum and maximum. the output voltage is lower than its average value during the rising phase of the input voltage and higher during the input voltage decay. similarly to the inpu t power and voltage, the frequency of the capacitor current (represented in the case of a resistive load) is twice the ac line on e.
and8123/d http://onsemi.com 16 in this calculation, one does not consider the switching ripple that is generally small compared to the low frequency ripple. in addition, the switching ripple depends on the load current shape that cannot be predicted in a general manner. as already discussed, the average coil current over a switching period is: (eq. 78) lin 2 * pin vac * sin( t) the instantaneous input power (averaged over the switching period) is the product of the input voltage (2 * vac * sin(
t) ) by iin. consequently: (eq. 79) pin 2* pin * sin 2 ( t) in average over the switching period, the bulk capacitor receives a charge current ( *pin vout) , where is the pfc stage efficiency, and supplies the averaged load current i2 * pin vout . applying the famous acapacitor formulao i c*dv dt , it becomes: (eq. 80) * pin vout i2 cbulk * dvout dt substitution of equation (79) into equation (80) leads to: (eq. 81) dvout dt 1 cbulk * 2* * pin * sin 2 ( t) vout * pin vout rearranging the terms of this equation, one can obtain: (eq. 82) vout * dvout dt * pin cbulk *
2 * sin 2 ( t) 1 noting that d(vout 2 ) dt 2 * vout * dvout dt and that cos(2 t) 1?2 * sin 2 ( t) , one can deduct the square of the output voltage from the precedent equation: (eq. 83) vout 2 vout 2 ? * pin cbulk * * sin(2 t) where is the average output voltage. dividing the terms of the precedent equations by the square of the average output voltage, it becomes: (eq. 84) vout vout 2 1 * pin * sin(2 t) cbulk * * vout 2 thus: (eq. 85) vout vout vout 1 * pin * sin(2 t) cbulk * * vout 2 where v out is the instantaneous output voltage ripple. equation (85) can be rearranged as follows: (eq. 86) vout vout * 1 * pin * sin(2 t) cbulk * * vout 2 1 one can simplify this equation considering that the output voltage ripple is small compared to the average output voltage (fortunately, it is generally true). this leads to say that the term 1 * pin * sin(2 t) cbulk * * vout 2 1 is nearly zero or in other words, that * pin * sin(2 t) cbulk * * vout 2 is small compared to 1. thus, one can write that: (eq. 87) 1 * pin *sin(2 t) cbulk * * vout 2 1 1 2 * pin * sin(2 t) cbulk * * vout 2
and8123/d http://onsemi.com 17 substitution of equation (86) into equation (87), leads to the simplified ripple expression that one can generally find in the literature: (eq. 88) vout ? * pin * sin(2 t) 2 * cbulk * * vout the maximum ripple is obtained when (sin(2
t) ?1) and minimum when (sin(2 t) 1) . thus, the peak?to?peak ripple that is the difference of these two values is: (eq. 89) ( vout)pk ? pk * pin cbulk * * vout and: (eq. 90) vout vout ( vout)pk?pk 2 * sin(2 t) conclusion compared to traditional switch mode power supplies, one faces an additional difficulty when trying to predict the currents and voltages within a pfc stage: the sinusoid modulation. this is particularly true in critical conduction mode where the switching ripple cannot be neglected. as proposed in this paper, one can overcome this difficulty by: ? first calculating their value within a switching period, ? then the switching period being considered as very small compared to the ac line cycle, integrating the result over the sinusoid period. the proposed theoretical analysis helps predict the stress faced by the main elements of the pfc stages: coil, mosfet, diode and bulk capacitor, with the goal of easing the selection of the power components and therefore, the pfc implementation. nevertheless, as always, it cannot replace the bench work and the reliability tests necessary to ensure the application proper operation.
and8123/d http://onsemi.com 18 figure 15. summary icoil_pk 2* 2 * pin vac *sin( t) peak coil current: maximum peak current: icoil_max 2* 2 * pin max vacll rms coil current: icoil(rms) 2 3 * pin vac f vac 2 2*l* pin 1 2 *vac*sin( t) vout switching frequency: psw 2*( t t fr )*vac 2 *l * vout 2 *vac 4 switching losses: pon 4 3 *ron* pin vac 2 *
1 8* 2 *vac 3 * vout conduction losses: id i load pout vout average diode current: id(rms) 4 3 * 2* 2 * pin vac * vout rms diode current: ac line l1 r5 m1 r7 controller d6 v out + c1 load i load MC33260 like current sense resistor (rs = r5) dissipation: prs 260 4*rs 3 * pin vac 2 mc33262 like current sense resistor (rs = r7) dissipation: prs 262 4 3 *rs* pin vac 2 *
1 8* 2 *vac 3 * vout capacitor low frequency ripple: ( vout)pk?pk * pin cbulk * * vout rms capacitor current: ic(rms) 32 * 2 * pin 2 9* * vac * vout
i load (rms) 2 if load is resistive: ic(rms)
32 * 2 9* * pin 2 vac * vout vout r 2 vac: ac line rms voltage vacll: vac lowest level : ac line angular frequency : average input power max: maximum pin level vout: output voltage pout: output power iload: load current iload(rms): rms load current : efficiency ron: mosfet on resistance t, t fr : switching times (see switching losses section and figure 10) cbulk = c1: bulk capacitor value rs: current sense resistance l: coil inductance
and8123/d http://onsemi.com 19 notes
and8123/d http://onsemi.com 20 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 and8123/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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